c3f404872e
First Phase 1 increment toward the single-device 3-in-1: one Heltec V3 (ESP32-S3 + single SX1262) rotating the radio through the Meshtastic / MeshCore / Reticulum PHY presets, logging every raw packet it demodulates per dwell window. No framing/crypto/bridge yet — proves the RX loop first. Validated on hardware: radio.begin() clean, all three presets cycle, and the Meshtastic window received live broadcast packets (-36..-41 dBm). The single-radio time-multiplex premise (ARCHITECTURE.md §2) holds. MeshCore sync word and Reticulum PHY are flagged placeholders in CONFIGS[]. Deps pinned (espressif32 7.0.1, RadioLib 7.7.1). Adds venv/pycache/storage to .gitignore. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
19 lines
612 B
INI
19 lines
612 B
INI
; archy-messh Phase 1 firmware — single Heltec WiFi LoRa 32 V3, one SX1262
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; time-multiplexed across the Meshtastic / MeshCore / Reticulum PHY configs.
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;
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; See ../docs/ARCHITECTURE.md §2-§3 for why Phase 1 is a single time-multiplexed
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; radio (Option A) rather than the 3-separate-boards host bridge of Phase 0.
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;
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; Versions pinned exactly — do not float.
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[env:heltec_wifi_lora_32_V3]
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platform = platformio/espressif32@7.0.1
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board = heltec_wifi_lora_32_V3
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framework = arduino
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monitor_speed = 115200
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monitor_filters = time, default
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build_flags =
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-D ARCHY_MESSH_FW
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lib_deps =
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jgromes/RadioLib@7.7.1
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