feat: Phase 1 firmware — time-multiplexed tri-protocol RX scanner
First Phase 1 increment toward the single-device 3-in-1: one Heltec V3 (ESP32-S3 + single SX1262) rotating the radio through the Meshtastic / MeshCore / Reticulum PHY presets, logging every raw packet it demodulates per dwell window. No framing/crypto/bridge yet — proves the RX loop first. Validated on hardware: radio.begin() clean, all three presets cycle, and the Meshtastic window received live broadcast packets (-36..-41 dBm). The single-radio time-multiplex premise (ARCHITECTURE.md §2) holds. MeshCore sync word and Reticulum PHY are flagged placeholders in CONFIGS[]. Deps pinned (espressif32 7.0.1, RadioLib 7.7.1). Adds venv/pycache/storage to .gitignore. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
co-authored by
Claude Opus 4.8
parent
dbfdf1c851
commit
c3f404872e
@@ -0,0 +1,18 @@
|
||||
; archy-messh Phase 1 firmware — single Heltec WiFi LoRa 32 V3, one SX1262
|
||||
; time-multiplexed across the Meshtastic / MeshCore / Reticulum PHY configs.
|
||||
;
|
||||
; See ../docs/ARCHITECTURE.md §2-§3 for why Phase 1 is a single time-multiplexed
|
||||
; radio (Option A) rather than the 3-separate-boards host bridge of Phase 0.
|
||||
;
|
||||
; Versions pinned exactly — do not float.
|
||||
|
||||
[env:heltec_wifi_lora_32_V3]
|
||||
platform = platformio/espressif32@7.0.1
|
||||
board = heltec_wifi_lora_32_V3
|
||||
framework = arduino
|
||||
monitor_speed = 115200
|
||||
monitor_filters = time, default
|
||||
build_flags =
|
||||
-D ARCHY_MESSH_FW
|
||||
lib_deps =
|
||||
jgromes/RadioLib@7.7.1
|
||||
Reference in New Issue
Block a user